1. Field of the Invention
The present invention relates to an automatic trace shaping method for automatically shaping existing traces consisting of straight and/or curved lines that are designed to be disposed in arbitrary directions on a surface of a substrate of a semiconductor package into traces each consisting of a combination of segments in predetermined directions by using computation.
2. Description of the Related Art
In LSI (Large-scale integrations), PCB (Printed-circuit boards) and the like, for example, as set forth in Jono, “An operating method of an integrated printed-circuit board CAD tool”, Design Wave Magazine, CQ Publishing Co., Ltd., June 2003, pp. 51-56, it is typical that a trace is comprised of a plurality of straight line segments and the trace is designed so that these segments lie in directions of 90 or 45 degrees.
The LSI and PCB have pattern characteristics which have relatively large spaces around the traces and disposed positions and the shapes of obstacles have a certain amount of regularity. The traces in an LSI, PCB and the like can be easily designed according to design rules that allow computation by a computer, and therefore, several automatic wiring methods have already been proposed.
For example, as a typical example of an automatic wiring method for an LSI and PCB, there is a method called a labyrinth search method as set forth in Japanese Unexamined Patent Publication No. 11-161694, Japanese Unexamined Patent Publication No. 2001-350813, Japanese Unexamined Patent Publication No. 2001-044288, or Japanese Unexamined Patent Publication No. 10-209288. In this labyrinth search method, trace routes on a substrate are set so as to secure clearance from obstacles and so as to not intersect the obstacles by bypassing such obstacles in the directions of 90 degrees or in some cases 45 degrees.
In contrast to this, on substrates of semiconductor integrated circuit mounting packages (hereinafter simply referred to as “semiconductor packages”) such as a PBGA, EBGA and the like, there are a large number of elements, such as planes, gates, marks, dummy pads, internal components or other traces in the packages and so on, that may obstruct the traces and shapes and the disposed positions or angles of such obstacles may vary significantly. Further, vias, balls, bonding pads (B/P), flip chip pads (F/C) or the like, which are to be starting or end points of the traces, may be positioned at various points, and moreover, sufficient space often cannot be secured around the traces. Therefore, in the trace design of semiconductor packages, traces are often disposed in directions of arbitrary angles on the surface of the substrate of the semiconductor package. In the trace design of semiconductor packages, a designer typically designs the trace routes of the semiconductor packages on a virtual plane by trial and error depending on the designer's skill, experience and intuition, for example, by using a CAD system.
For example, as a trace design method for semiconductor packages, there has been proposed an automatic wiring method that uses a CAD system for generating, by automatic computation, trace shapes satisfying design rules, for example, by generating circular arcs around vias according to the design rules and combining the traces based on the tangents of the circular arcs, as set forth in Japanese Unexamined Patent Publication No. 2002-083006.
Further, for example, there has been proposed a semi-automatic wiring method that does not rely on automatic computation, but generates an outlined route manually and determines an optimal route when semiconductor elements other than two or more semiconductor elements between which a trace route is intended to be set are assumed to be obstacles, as set forth in Japanese Unexamined Patent Publication No. 09-069118.
Still further, there has been proposed a trace design method of semiconductor packages that implements traces in directions of specific angles, as set forth in Japanese Unexamined Patent Publication No. 05-055305.
As described above, when traces in arbitrary directions (at arbitrary angles), for example, traces comprised of straight and/or curved lines, are designed in semiconductor packages, a CAD that complies with such trace design is typically used for the semiconductor packages. In contrast, a CAD for an LSI is good at designing traces that consist of a combination of segments in the direction of “45×n” degrees (where n is an integer) with respect to a predetermined reference line (hereinafter also referred to as “45-degree traces” or “inclined 45-degree traces”), but is weak in designing curved traces in arbitrary directions. In other words, there is no compatibility between trace design data designed by a CAD for semiconductor packages and that designed by a CAD for an LSI. Generally, traces in circuit boards are often designed by using a CAD for an LSI, and in this case, even though the trace design for semiconductor packages has already been completed, the traces have to be redesigned so that the trace design can also be utilized in a CAD for an LSI.
Further, in order to implement the 45-degree traces described above by using a CAD for semiconductor packages, the designer has to set the direction in which the traces can be disposed at 45 degrees in the CAD software for semiconductor packages, and while viewing a display screen, has to manually design each segment or each trace one by one by trial and error so as to satisfy requirements for clearance (lines and spaces). The traces on the surface of the substrates of semiconductor packages are very dense and it is difficult to secure sufficient space around the traces, and therefore, it is difficult to implement 45-degree traces.
In the manual trace design by trial and error as described above, as traces become more complicated, the effort, time and difficulty for achieving optimal traces is increased. Further, an unevenness in quality of finished products in which traces have been designed is also increased. In reality, because manual trace design by trial and error requires 3-10 days for one product, it is not economical and requires a compromise of design quality.
In view of the above problems, it is an object of the present invention to provide an automatic trace shaping method that can automatically shape existing traces consisting of straight and/or curved lines that are designed to be disposed in arbitrary directions on the surface of a substrate of a semiconductor package into traces which consist of a combination of segments having specific angles with respect to a predetermined reference line.